The present invention relates to a solid state image sensor utilizing a static induction transistor (hereinafter, abbreviated as SIT) as an image pick-up element.
As a conventional solid state image sensor for use in video camera, facsimile etc. there has been proposed a charge transfer device such as BBD, CCD etc. or a MOS transistor device. However, these solid state image sensors have various disadvantages such as charge leakage during the charge transferring operation and a low sensitivity of light detection.
Recently, in order to eliminate the disadvantages mentioned above, there has been proposed a solid state image sensor comprising SITs. The SIT is a kind of phototransistor having both a photo-electrical converting function and a photoelectric charge storing function, and has various advantages such as high input impedance, high speed property, unsaturated property, low noise, low consumed power etc., as compared with a field effect transistor or a junction transistor. Therefore, if use is made of the SIT as a solid state image pick-up element, it is possible to form a solid state image sensor having high sensitivity, high speed response and wide dynamic range.
Such image sensor has been disclosed in the Japanese Patent Laid-Open Publication No. 105,672/83 published on June 23, 1983.
FIG. 1 is a cross sectional view showing one embodiment of the SIT consisting of one pixel of the known solid state image sensor. In this embodiment, an SIT 1 has a vertical type construction in which a drain region is constructed by an n.sup.+ substrate 2 and a source region is constructed by an n.sup.+ region 4 formed in an n.sup.- epitaxial layer 3 which is formed on the n.sup.+ substrate 2 and constitute a channel region. In the epitaxial layer 3 there is further formed a P.sup.+ signal storing gate region 5 surrounding the n.sup.+ source region 4, and on the gate region 5 is formed an electrode 7 via an insulating film 6. In this manner, a gate electrode is provided having a so-called MIS construction consisting of metal electrode/insulating film/semiconductor gate region. Moreover, the impurity concentration in the n.sup.- epitaxial layer 3 which constructs the channel region is set to such a low level that the channel region is depleted even if a bias applied to the gate electrode 7 is 0 V so that a pinch-off voltage due to a high potential barrier can be obtained.
Hereinafter, the operation of the SIT 1 mentioned above will be explained. When light is made incident upon the channel region 3 and the gate region 5 under the condition that a bias is not applied between the drain and source, holes of electron-hole pairs induced thereat are stored in the gate region 5 and electrons are discharged from the drain region 2 to the ground. The holes stored in the gate region 5 in response to the incident light function to increase a potential of the gate region 5 and to decrease the potential barrier of the channel region 3 in response to the incident light intensity. If the bias voltage is applied between the drain and source and also a foward bias voltage is applied to the gate electrode 7, a current flows between the drain and source in response to the amount of holes stored in the gate region 5 and thus the output amplified in accordance with the incident light intensity can be obtained. The light amplification S is described as follows, EQU S.varies.(l.sub.1 .times.l.sub.2)/a.sup.2
where 2a is an inner diameter of the ring-shaped gate region 5, l.sub.1 is a depth of the gate region 5 and l.sub.2 is a distance between the gate and drain regions. In the SIT 1 mentioned above, the value of the light amplification S is normally greater than 10.sup.3, and is higher by one order than that of a bipolar transistor. As can be seen from the above, in order to obtain a higher light amplification, it is necessary to make the distance 2a small and to make the depth of the epitaxial layer 3 and that of the gate region 5 large. For example, in order to obtain a light amplification S of 10.sup.3 to 10.sup.4, it is necessary to satisfy the condition that l.sub.1 =2 to 3 .mu.m and l.sub.2 =5 to 6 .mu.m.
In the solid state image sensor mentioned above, it is necessary to arrange an isolation region 8 between adjacent SITs so as to isolate the signal charges induced in respective SITs. This isolation is realized by a normal isolation method such as oxide film isolation, diffusion isolation or V-shape recess isolation. In this case, the isolation region 8 extends from a surface of the epitaxial layer 3 to the substrate 2, and thus it is difficult to form the isolation region 8 if the epitaxial layer 3 is thick. Moreover, as mentioned above, it is necessary to make the gate region 5 thick so as to increase the light amplification S, but this is not realized by the diffusion method. Further, if the gate region 5 is made thicker, the spectral sensitivity property becomes worse due to the absorption of light in the gate region 5. Therefore, in the known solid state image sensor consisting of vertical type SITs, the sensitivity is limited due to the construction thereof.
Moreover, in case of effecting a self-alignment process for integrating the source-gate construction, it is necessary to cover the source region 4 with a mask when the gate region 5 is formed. Therefore, the above process becomes complicated and expensive. Moreover, if the source-gate construction is integrated, a breakdown voltage between the source and drain becomes low so that the leak current might be increased to a great extent.